The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device whose package combines high power dissipation with a small footprint.
Modern semiconductor technology is producing integrated circuits containing up to several million transistors. Such high integration levels provide increased functionality while creating the problem of dissipating the power generated by the large number of transistors. Portable equipment such as pagers and cellular telephones benefit from the increased functionality but also create a need to reduce the physical size of these integrated circuits to fit within their smaller housings.
The physical size of many integrated circuits often is determined by the area needed for providing hundreds of package terminals whose dimensions are configured for mounting on a system circuit board because the minimum feature size of a system circuit board is larger than that of an integrated circuit. For example, integrated circuits are commercially available whose input/output interconnect pitch is less than 0.1 millimeters, whereas interconnect traces for mounting the integrated circuit on a system circuit board are formed with a pitch of about 0.4 millimeters, more than 4 times larger.
To provide a large number of terminals in a small package area, chip scale packages have been developed which consume nearly the same area on the circuit board as the area of the encapsulated die. For example, a chip scale package for housing a square die 10.0 millimeters on a side typically occupies an area between 10.0 and 16.0 millimeters on a side. The small footprint is achieved by forming die mounting flags on the interposer which are aligned with and soldered to the bonding pads of the die in a "flip-chip" fashion. The die mounting flags are coupled with wiring traces to more loosely spaced package terminals of the interposer. The die can be encapsulated in a molding compound for protection.
A problem with prior art chip scale packages is high thermal resistance due to their small area and the low thermal conductivity of the interposer substrate, which limits the power dissipation of the device. In addition, such high thermal resistance can result in damage to the integrated circuit from elevated temperatures created by power dissipated by nearby components. Heat sinks could be mounted on the package to reduce the die temperature, but heat sinks increase the package footprint and induce mechanical stress on the package which can adversely affect the reliability of the device.
Hence, there is a need for a small footprint semiconductor device with increased power handling capability.